

{"id":612,"date":"2022-03-31T15:07:28","date_gmt":"2022-03-31T19:07:28","guid":{"rendered":"https:\/\/sites.temple.edu\/silage\/?page_id=612"},"modified":"2024-10-04T16:21:10","modified_gmt":"2024-10-04T20:21:10","slug":"workshops","status":"publish","type":"page","link":"https:\/\/sites.temple.edu\/silage\/workshops\/","title":{"rendered":"Workshops"},"content":{"rendered":"<p><em><strong><span style=\"color: #9f0009\">Mini-Workshop on Software Defined Radio Using the RTL-SDR<a href=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/IEEE-Philadelphia-Section-2.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"alignright size-medium wp-image-637\" src=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/IEEE-Philadelphia-Section-2-300x105.jpg\" alt=\"\" width=\"300\" height=\"105\" srcset=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/IEEE-Philadelphia-Section-2-300x105.jpg 300w, https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/IEEE-Philadelphia-Section-2.jpg 398w\" sizes=\"auto, (max-width: 300px) 100vw, 300px\" \/><\/a><\/span><\/strong><\/em><\/p>\n<p>Sponsored by the IEEE Philadelphia Section and IEEE-USA.<\/p>\n<p style=\"text-align: justify\"><img loading=\"lazy\" decoding=\"async\" class=\"size-medium wp-image-628 alignleft\" src=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/03\/IEEE-USA-300x64.png\" alt=\"\" width=\"300\" height=\"64\" srcset=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/03\/IEEE-USA-300x64.png 300w, https:\/\/sites.temple.edu\/silage\/files\/2022\/03\/IEEE-USA.png 403w\" sizes=\"auto, (max-width: 300px) 100vw, 300px\" \/>The software defined radio (SDR) is the modern evolution of the hardware approach to radio communications that had dominated recent technology. Discrete components formerly implemented tuned circuits, amplifiers, oscillators, mixers and detectors to provide analog modulation and demodulation. Even though vacuum tube electronics gave way to transistors and integrated circuits, the components of the radio remained discrete. However, the advent of digital modulation and application specific integrated circuits has resulted in an SDR in which all but the front end of the receiver and the back end of the transmitter could be accomplished with digital signal processing software. This Mini-Workshop presents the progression of the configuration and the availability of inexpensive SDRs that, while only capable of reception, can still provide an experience in wireless technology.<a href=\"https:\/\/sites.temple.edu\/silage\/files\/2023\/03\/RTl-SDR2.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"alignright wp-image-709\" src=\"https:\/\/sites.temple.edu\/silage\/files\/2023\/03\/RTl-SDR2.jpg\" alt=\"\" width=\"280\" height=\"96\" \/><\/a><\/p>\n<p>Mini-Workshop topics include:<\/p>\n<p>Signals and Systems<br \/>\nI\/Q Signals and the SDR<img loading=\"lazy\" decoding=\"async\" class=\"alignright wp-image-711\" src=\"https:\/\/sites.temple.edu\/silage\/files\/2023\/03\/RTL-SDR1-300x193.jpg\" alt=\"\" width=\"410\" height=\"264\" srcset=\"https:\/\/sites.temple.edu\/silage\/files\/2023\/03\/RTL-SDR1-300x193.jpg 300w, https:\/\/sites.temple.edu\/silage\/files\/2023\/03\/RTL-SDR1.jpg 681w\" sizes=\"auto, (max-width: 410px) 100vw, 410px\" \/><br \/>\nRTl-SDR Configuration<br \/>\nRTL-SDR Applications<br \/>\nAnalog and Digital Signal Spectra<br \/>\nAdditional Topics: Antenna Construction, RTL-SDR and GNU Radio, Resources and References<\/p>\n<p><em><strong><span style=\"color: #9f0009\">Mini-Workshop Materials<\/span><\/strong><\/em><\/p>\n<p>Mini-Workshop PowerPoints (pdf) are available. Send a request to <em><span style=\"color: #0000ff\"><a style=\"color: #0000ff\" href=\"mailto:silage@temple.edu\">silage@temple.edu<\/a><\/span><\/em><\/p>\n<p>&nbsp;<\/p>\n<p><span style=\"color: #9f0009\"><em><strong>Xilinx Zynq <span style=\"color: #9f0009\">System-on-Chip<\/span> Design Workshop <a href=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/IEEE-Philadelphia-Section-2.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"alignright size-medium wp-image-637\" src=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/IEEE-Philadelphia-Section-2-300x105.jpg\" alt=\"\" width=\"300\" height=\"105\" srcset=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/IEEE-Philadelphia-Section-2-300x105.jpg 300w, https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/IEEE-Philadelphia-Section-2.jpg 398w\" sizes=\"auto, (max-width: 300px) 100vw, 300px\" \/><\/a><\/strong><\/em><\/span><\/p>\n<p><span style=\"color: #000000\">Sponsored by the IEEE Philadelphia Section and IEEE-USA.<\/span><\/p>\n<p style=\"text-align: justify\"><a href=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/03\/IEEE-USA.png\"><img loading=\"lazy\" decoding=\"async\" class=\"size-medium wp-image-628 alignleft\" src=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/03\/IEEE-USA-300x64.png\" alt=\"\" width=\"300\" height=\"64\" srcset=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/03\/IEEE-USA-300x64.png 300w, https:\/\/sites.temple.edu\/silage\/files\/2022\/03\/IEEE-USA.png 403w\" sizes=\"auto, (max-width: 300px) 100vw, 300px\" \/><\/a><span style=\"color: #000000\">The Xilinx Zynq System-on-Chip (SoC) provides a dual ARM Cortex-A9 32-bit processor with floating point, DRAM and Flash controllers,\u00a0peripheral interfaces, an AMBA interconnection bus and programmable logic with RAM and DSP om a single device. The Xilinx Vivado HLx Webpack suite provides the hardware and software design environment for the configuration and C language programming of the Zynq device. The Digilent Zybo board utilizes the Zynq device and provides peripherals, DRAM, I\/O ports, audio codec and Ethernet and USB ports.<\/span><\/p>\n<p style=\"text-align: justify\"><span style=\"color: #000000\">The Workshop introduces the participants to the design process for the SoC using Vivado HLx and the Zybo board. The participants will perform han<a style=\"color: #000000\" href=\"https:\/\/sites.temple.edu\/silage\/files\/2014\/10\/Zynq.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"alignright wp-image-567\" src=\"https:\/\/sites.temple.edu\/silage\/files\/2014\/10\/Zynq-272x300.jpg\" alt=\"\" width=\"275\" height=\"303\" srcset=\"https:\/\/sites.temple.edu\/silage\/files\/2014\/10\/Zynq-272x300.jpg 272w, https:\/\/sites.temple.edu\/silage\/files\/2014\/10\/Zynq.jpg 520w\" sizes=\"auto, (max-width: 275px) 100vw, 275px\" \/><\/a>ds-on designs of process control systems with actuator and display and FIR digital filtering with ADC and DAC serial peripheral interface (SPI) modules. The Workshop utilizes\u00a0<em>The\u00a0<\/em>Z<em>ynq Book Tutorial<\/em>\u00a0and considers AMBA bus AXI-lite interfacing and software timers.<\/span><\/p>\n<p><span style=\"color: #9f0000\"><em><strong>Workshop materials:<\/strong><\/em><\/span><\/p>\n<p><span style=\"color: #0000ff\"><span style=\"color: #000000\"><em><span style=\"color: #0000ff\"><a style=\"color: #0000ff\" href=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/05\/Installation-of-Xilinx-Vivado-SDK-and-Zynq-Projects.pdf\">Installation of Xilinx Vivado SDK and Zynq Projects (pdf)<\/a><\/span><\/em>\u00a0This is the instruction on how to download and install Xilinx Vivado 2019.1 as <em>C:\\Xilinx\u00a0<\/em>and the installation of the material listed below.<\/span><\/span><\/p>\n<p><em><a href=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/The_Zynq_Book-1.pdf\"><span style=\"color: #0000ff\">The_Zynq_Book (pdf)\u00a0<\/span><\/a><\/em> <span style=\"color: #000000\">Xilinx Zynq Book reference material. Unzip and store conveniently as <em>Documents\\Zynq Book.<\/em><\/span><br \/>\n<em><span style=\"color: #0000ff\"><a style=\"color: #0000ff\" href=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/The_Zynq_Book_Tutorials.pdf\">The_Zynq_Book_Tutorial (pdf)\u00a0<\/a> \u00a0<\/span><\/em><span style=\"color: #000000\">Xilinx Zynq Book Tutorials used in the Workshop as a reference. Unzip and store conveniently as <em>Documents\\Zynq Book.<\/em><\/span><br \/>\n<span style=\"color: #0000ff\"><a style=\"color: #0000ff\" href=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/Zynq_Book_Sources.zip\"><em>Zynq_Book_Sources (zip)\u00a0 <\/em><\/a><\/span><span style=\"color: #000000\">Zynq Book C language source code for the Tutorials in SDK. Unzip and store the folder as <em>C:\\Zynq_Book_Sources<\/em><\/span><\/p>\n<p><strong><em><span style=\"color: #0000ff\"><a href=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/data-boards-board_parts.zip\"><span style=\"color: #0000ff\">data boards board parts<\/span><\/a> (zip)\u00a0 <\/span><\/em><\/strong><span style=\"color: #000000\">Unzip and store the subfolders on <\/span><em><span style=\"color: #000000\">C:\\Xilinx\\Vivado\\2019.1\\data\\boards\\board_parts<\/span><\/em><br \/>\n<span style=\"color: #0000ff\"><em><a style=\"color: #0000ff\" href=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/data-boards-board_files.zip\">data boards board files (zip)\u00a0<\/a><\/em> \u00a0<span style=\"color: #000000\">Unzip and store the subfolders on <\/span><em><span style=\"color: #000000\">C:\\Xilinx\\Vivado\\2019.1\\data\\boards\\board_files<\/span><\/em><\/span><\/p>\n<p><a href=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/first_zynq_design.zip\"><span style=\"color: #0000ff\"><em>first_zynq_design (zip)\u00a0<\/em> <\/span>\u00a0<\/a> <a href=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/zynq_interrupts.zip\"><em><span style=\"color: #0000ff\">zynq_interrupts (zip)\u00a0 \u00a0<\/span><\/em> \u00a0<\/a><em><span style=\"color: #0000ff\"><a style=\"color: #0000ff\" href=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/ip_repo.zip\">ip_repo (zip)<\/a><\/span><\/em><a href=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/zynq_interrupts.zip\"> \u00a0\u00a0\u00a0 <\/a><em><span style=\"color: #0000ff\"><a style=\"color: #0000ff\" href=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/zynq_add_interrupts.zip\">zynq_add_interrupts (zip)<\/a><\/span><\/em><a href=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/zynq_interrupts.zip\"><em><span style=\"color: #0000ff\"> \u00a0\u00a0<\/span><\/em>\u00a0 <\/a><a href=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/led_controller.zip\"><span style=\"color: #0000ff\"><em>led_controller (zip)<\/em><\/span>\u00a0<\/a>These are the subfolders for the folder <em>Zynq_Book_Tutorial_Solutions.\u00a0<\/em>Unzip each of these subfolders and store as C:\\<em>Zynq_Book_Tutorial_Solutions. <\/em>See\u00a0the <em>Installation<\/em> and <em>Workshop PowerPoints<\/em> for more details.<a href=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/led_controller.zip\">\u00a0\u00a0<\/a><\/p>\n<p><span style=\"color: #0000ff\"><em><a style=\"color: #0000ff\" href=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/zybo-z7_rm.pdf\">zybo-z7_rm (pdf)<\/a>\u00a0 \u00a0<\/em><\/span> <em><a href=\"https:\/\/sites.temple.edu\/silage\/files\/2022\/04\/cora_z7_rm.pdf\"><span style=\"color: #0000ff\">cora_z7_rm (pdf)<\/span><\/a><\/em> \u00a0These are the reference manuals for the Workshop Digilent Zybo board and the continuing education Digilent Cora Z7 board<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Mini-Workshop on Software Defined Radio Using the RTL-SDR Sponsored by the IEEE Philadelphia Section and IEEE-USA. The software defined radio (SDR) is the modern evolution of the hardware approach to radio communications that had dominated recent technology. Discrete components formerly implemented tuned circuits, amplifiers, oscillators, mixers and detectors to provide analog modulation and demodulation. Even &hellip;<\/p>\n","protected":false},"author":5636,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-612","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/sites.temple.edu\/silage\/wp-json\/wp\/v2\/pages\/612","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/sites.temple.edu\/silage\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/sites.temple.edu\/silage\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/sites.temple.edu\/silage\/wp-json\/wp\/v2\/users\/5636"}],"replies":[{"embeddable":true,"href":"https:\/\/sites.temple.edu\/silage\/wp-json\/wp\/v2\/comments?post=612"}],"version-history":[{"count":16,"href":"https:\/\/sites.temple.edu\/silage\/wp-json\/wp\/v2\/pages\/612\/revisions"}],"predecessor-version":[{"id":749,"href":"https:\/\/sites.temple.edu\/silage\/wp-json\/wp\/v2\/pages\/612\/revisions\/749"}],"wp:attachment":[{"href":"https:\/\/sites.temple.edu\/silage\/wp-json\/wp\/v2\/media?parent=612"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}