{"id":10,"date":"2015-04-14T17:43:03","date_gmt":"2015-04-14T21:43:03","guid":{"rendered":"https:\/\/sites.temple.edu\/silage\/?page_id=10"},"modified":"2025-12-23T18:36:17","modified_gmt":"2025-12-23T23:36:17","slug":"text-books","status":"publish","type":"page","link":"https:\/\/sites.temple.edu\/silage\/text-books\/","title":{"rendered":"Text Books"},"content":{"rendered":"

Digital Communication Systems Using <\/span><\/i><\/strong>SystemVue<\/strong>\"BookCover\"<\/a><\/span><\/span>
\nDa Vinci Engineering Press, Thomson Delmar Publishing 2006<\/span><\/span><\/p>\n

SystemVue <\/i>models of baseband and bandpass modulation and demodulation syste<\/span>ms, time, frequency and code division multiplexing, synchronization and equalization, channel models, frequency hopping and discrete sequence spread spectrum, orthogonal frequency division multiplexing and baseband and bandpass signal sampling in digital communication system design.<\/span><\/span><\/p>\n

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Digital Communication Systems Using MATLAB and Simulink – Second Edition\"MS2cover\"<\/span><\/a><\/i><\/span>
\nBookstand Publishing 2016 (First Edition\u00a0<\/em>2009)<\/span><\/span><\/p>\n

MATLAB and Simulink <\/i>models of analog AM and FM, baseband and bandpass binary and M-ary modulation and demodulation systems, time, frequency and code division multiplexing, frequency hopping and discrete sequence spread spectrum, orthogonal frequency division multiplexing, line codes, and baseband and bandpass signal sampling in digital communication system design. Text models are available as Chapter folders and in password protected files: Digital Communication Simulation 2nd Ed using MATLAB and Simulink<\/a><\/em><\/span><\/span><\/p>\n

 <\/p>\n

Embedded Design Using Programmable Gate Array<\/i><\/span><\/strong>s<\/span><\/strong>
\n<\/span><\/a><\/i>Bookstand Publishing, 2008\"EDPGABookFront\"
\n<\/span><\/p>\n

Embedded design with behavioral synthesis controller-datapath models in Verilog, C-to-Verilog translation, Xilinx LogiCORE blocks and the PicoBlaze 8-bit soft-core processor utilizing the Xilinx Spartan-3E field programmable gate array evaluation boards, the Xilinx ISE WebPACK and applications in digital signal processing, communications and control. Text models are available from the author by email.<\/span><\/p>\n

 <\/p>\n

 <\/p>\n

Trends in E<\/span><\/span><\/i><\/a>mbedded Design Using Programmable Gate Arrays<\/a><\/i><\/span>
\n<\/i><\/span><\/span>Bookstand Publishing, 2013\"TrendsEDPGAcover\"<\/span><\/p>\n

Embedded design with behavioral synthesis controller-datapath models in Verilog, C-to-Verilog translation, Xilinx LogiCORE blocks utilizing the Xilinx Spartan-6 field programmable gate array evaluation boards, the Xilinx ISE and applications of advanced sensors in digital signal processing, communications and control and a description of the Xilinx Zynq Extensible Processing Platform. Text models are available from the author by email.<\/i><\/span><\/p>\n","protected":false},"excerpt":{"rendered":"

Digital Communication Systems Using SystemVue Da Vinci Engineering Press, Thomson Delmar Publishing 2006 SystemVue models of baseband and bandpass modulation and demodulation systems, time, frequency and code division multiplexing, synchronization and equalization, channel models, frequency hopping and discrete sequence spread spectrum, orthogonal frequency division multiplexing and baseband and bandpass signal sampling in digital communication system …<\/p>\n","protected":false},"author":5636,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-10","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/sites.temple.edu\/silage\/wp-json\/wp\/v2\/pages\/10","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/sites.temple.edu\/silage\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/sites.temple.edu\/silage\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/sites.temple.edu\/silage\/wp-json\/wp\/v2\/users\/5636"}],"replies":[{"embeddable":true,"href":"https:\/\/sites.temple.edu\/silage\/wp-json\/wp\/v2\/comments?post=10"}],"version-history":[{"count":15,"href":"https:\/\/sites.temple.edu\/silage\/wp-json\/wp\/v2\/pages\/10\/revisions"}],"predecessor-version":[{"id":760,"href":"https:\/\/sites.temple.edu\/silage\/wp-json\/wp\/v2\/pages\/10\/revisions\/760"}],"wp:attachment":[{"href":"https:\/\/sites.temple.edu\/silage\/wp-json\/wp\/v2\/media?parent=10"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}