The SCDL performs innovative research with reconfigurable processing architectures in the field programmable gate array (FPGA) and system-on-chip (SoC) devices. The virtexXilinx Virtex I FPGA was investigated beginning in 2002 as an exemplar of a  fine-grained FPGA architecture. A fine-grained FPGA architecture is a configuration of a large number of the nearly the same processing elements or control logic blocks (CLB). The Virtex I represented a significant improvements in performance, logic density, and power efficiency by optimizing the fine-grained programmable logic and routing architecture of the FPGA.

Next, further improvements were made by embedding coarse-grained elements such as memories, multipliers, and processors within the fine-grained programmable fabric of the FPGA. Coarse-grained elements can implement a specific function more efficiently than fine-grained programmable logic.

The coarse-grained Xilinx Virtex II Pro FPGA was investigated beginning in 2005. An innovation of the Virtex II Pro was the inclusion of an IBM PowerPC 405 hardcore processor with the VirtexIIcoarse-grained FPGA. The interface between the hardcore processor and the FPGA was the research focus in this interval.

If this interface is not flexible, the usefulness of the hardcore processor is compromised. Alternatively if the interface is too flexible, it will require too much area and resulting delay and latency. This was shown by behavioral simulation and synthesis studies to affect the performance advantages of the hardcore processor within the FPGA.

The SCDL, in implementing the concept of algorithms into hardware, next began to investigate digital signal and digital image processing tasks in the coarse-grained Xilinx Virtex-4 and Virtex-5 FPGA.

Rapid Hardware/Software Codesign -click to expand

An integrated design environment (IDE) was developed to facilitate the rapid hardware/software co-design of a digital signal processor (DSP) or process control soft core   (Rapid Hardware/Software Co-Design of Programmable Gate Array Processor Architecture, Andrew Whitworth 2008).

Utilizing the Xilinx System Generator for DSP software and the MathWorks MATLAB/Simulink graphical programming environment, processor components were formulated in terms of compatible library modules where performance, capabilities, resource usage, and critical path timing can be altered. A dynamically configurable and conversational assembler was also developed that can generate processor machine code for an expansive range of hardware configurations.

Xilinx System Generator – click to expand

Based on this experience with the Xilinx System Generator for DSP and the MathWorks MATLAB/Simulink graphical programming environment, the SCDL continued to develop hardware-in-the-loop and embedded processing for investigations in digital communications (Parallel Implementation of Adaptive Frequency Domain Channel Equalization Using a Programmable Gate Array. John Mountney, 2007; Turbo Coding Implemented in a Coarse-Grained Programmable Gate Array Architecture, Robert Esposito, 2008; Evaluation of Space Time Block Codes Under Controlled Fading Conditions Using Hardware Simulation, Leonard Colavito 2009), digital image processing (Computational Acceleration for Next Generation Chemical Standoff Sensors Using the FPGA, John Ruddy, 2011) and neural signal processing (Particle Filtering Programmable Gate Array Architecture for Brain Machine Interfaces, John Mountney, 2011).

Zynq SoC – click to expand

Starting in 2012, the SCDL began to investigate the Xilinx Zynq System-on-Chip (SoC) device. The Zynq integrates a dual ARM Cortex-A9 hardcore processor, coarse-grained FPGA and peripherals. The Zynq architecture differs from previous implementations of programmable logic and embedded processoSoC1rs by moving from an FPGA-centric platform to a processor-centric model and incorporating an AMBA bus interface.

This research is continuing and has produced benchmarking studies of the Zynq SoC (Rhealstone Benchmarking of FreeRTOS and the Xilinx Zynq Extensible Processing Platform, Timothy Boger, 2013; Performance of the Xilinx Zynq System-on-Chip Interconnect with Asymmetric Multiprocessing, Andrew Powell, 2014).; Statistical Performance of the ARM Cortex A9 Accelerator Coherency Port in the Xilinx SoC for Real-Time Applications, Andrew Powell and Dennis Silage, 2015).

Current research is concerned with the real-time data transfer performance of the AMBA bus of the Zynq SoC and the development of a message passing hardware augmentation integrated with the FreeRTOS operating system. The research has produced several benchmarks of performance for real-time computation in digital communications.