- ECE3622 Embedded System Design
The Xilinx Zynq System-on-Chip (SoC) device undergraduate ECE course PowerPoints in PDF format are available here: Zynq Book Tutorials and Zynq Book Tutorials II This course material utilizes The Zynq Book and The Zynq Book Tutorials which can be downloaded in PDF format at The Zynq Book and Tutorial webpage. This course also now features the FreeRTOS multi-tasking, real-time operating system as part of the curriculum.
Embedded System Design
The System Chip Design Lab is extending its educational mission to the analysis and design of modern embedded systems for digital signal processing, digital control, and digital data communication using the field programmable gate array (FPGA) and system-on-chip (SoC) devices. The FPGA has traditionally provided support for embedded system design by implementing a controller and data path algorithmic state machine.
Although microprocessor-based computer systems have usually been used for the design of larger scale embedded systems, the paradigm of the FPGA now challenges that notion of such a fixed architecture especially with the constraints of real-time. An inexpensive FPGA, such as the Xilinx Spartan-3E and Spartan-6, can provide a microprocessor in a hardware description language behavioral synthesis as a soft core processor with architectural features, such as the number of registers, arithmetic logic units, external memory and peripheral address decoding and data communication, customized for the task.
Alternatively, the Xilinx Zynq SoC provides a dual hard core processor, embedded peripheral controllers and the FPGA on a single device.
These texts are intended as a supplementary text and laboratory manual for undergraduate students in a contemporary course in digital logic and embedded systems. Professionals who have not had an exposure to the coarse-grained FPGA, the Verilog hardware description language (HDL), an electronic design automation (EDA) software tool or the new paradigm of the controller and datapath and the finite state machine (FSM) will find that these texts and the Digilent Xilinx FPGA boards provide the necessary experience in this emerging area of electrotechnology. The development of these texts were supported by the Xilinx University Program.
These text describes the analysis and design of modern embedded systems using the FPGA. This new paradigm in embedded system design describes the Verilog behavioral synthesis in digital signal processing (DSP), digital communications, digital control and data communication utilizing the FPGA, the integration of external interface hard peripherals and the implementation of a custom internal soft core peripherals and soft core processors.
The transition to embedded system design now in the massively parallel and fine grained architecture of the modern FPGA is described in these texts also by the translation of C/C++ program segments for real-time processing to a controller and datapath architecture or an algorithmic state machine. Finally, the availability of the Xilinx 8-bit PicoBlaze and 32-bit MicroBlaze soft core processors now also challenges the conventional microprocessor with its fixed architecture for embedded system design.
The Embedded Design Using Programmable Gate Arrays text features the Xilinx Spartan-3E™ FPGA and the Digilent Basys Board and the Spartan-3E Starter Board, the Xilinx Integrated Synthesis Environment (ISE) WebPACK design environment in Verilog HDL, theXilinx CORE Generator for LogiCORE Verilog modules and the Xilinx Embedded Development Kit (EDK) for the Xilinx 8-bit PicoBlaze soft core processor. The complete Xilinx ISE WebPACK Verilog source code modules for the projects delineated in the text and executing on the the Spartan-3E Starter Board are provided.
Trends in Embedded Design Using Programmable Gate Arrays, Bookstand Publishing, 2013, ISBN 978-1-61863-541-9, 320 pages
The Trends in Embedded Design Using Programmable Gate Arrays text features the Xilinx Spartan-6 FPGA and the Digilent Nexys 6 Board and the Atlys Board, the Xilinx Integrated Synthesis Environment (ISE) WebPACK design environment in Verilog HDL, the Xilinx CORE Generator for LogiCORE Verilog modules. The Xilinx Zynq SoC with dual ARM Cortex-A9 hard core processors, AMBA AXI bus and FPGA is described. The complete Xilinx ISE WebPACK Verilog source code modules for the projects delineated in the text and executing on the the Atlys Board are provided.