The theme of the System Chip Design Laboratory is algorithms into vectorhardware. This theme captures the concept that signal and data processing executing sequentially on a conventional device can be enhanced by the unique vector and parallel processing capabilities of the field programmable gate array (FPGA).

Conventional processors are generally scalar and sequential, albeit with pipeline architectures, floating point operations and higher speed logic compared to an FPGA. Alternatively, the FPGA can execute in parallel as a vector operation but usually with fixed point operations which require quantization analysis of the algorithm to be implemented. The MathWorks Fixed Point Designer™ facilitates this analysisalgorithms1 and the FPGA can use registers of any practical and of different sizes throughout the stages of the processing of the algorithm.

The Fixed-Point Designer provides data types and tools for developing fixed-point algorithms and automatically proposes fixed-point data types and attributes such as word length, the fixed point rounding mode and the action to be taken on register overflow. Bit-true simulations are then used to observe the impact of the limited range and precision. The Fixed-Point Designer converts floating-point algorithms to fixed point by specifying fixed-point data types that meet the numerical accuracy requirements and hardware constraints.

The tools and techniques for fixed point design in FPGAs were presented to the Philadelphia Chapter of the IEEE Circuits and System Society and the IEEE Computer Society and the presentation is available here.

FixedPoint1
Float-to-Fixed Point Algorithms – click to expand

Although fixed point algorithms have reasonable applications, floating point arithmetic, conventionally the realm of the processor, is also now a capability of the FPGA. Floating point algorithms support a large dynamic range and a simple design process. The Xilinx Artix-7 and Kintex-7  FPGA can provide to 1.33 teraflops of single-precision floating-point performance. An inherent simple design process for a floating point algorithm is enabled by the Xilinx System Generator for DSP™ from within the MathWorks Simulink modeling environment. The Xilinx System Generator for DSP also has the flexibility of optimizing an implementation that is bit- and cycle-accurate to the original model (High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs, Xilinx WP409).

 SystemGenerator