The System Chip Design Laboratory (SCDL, formerly the SCDC) of the Department of Electrical and Computer Engineering at Temple University was initiated in 1999 by The Western Design Center, Inc., an innovator in the development of microprocessor and peripheral intellectual property. SCDL is a educational and research facility of Department of Electrical and Computer Engineering in the College of Engineering. SCDL is a direct descendant of the Advanced Processor Systems Laboratory (APSL) which was established in 1987, supported by Intel and utilized the Intel iRMX III real-time, multitasking operating system (RTOS) executing on the Intel Multibus II multiprocessor computer. Research developed message passing nucleus system calls for the iRMX III RTOS for the AT&T Microelectronics DSP32C digital signal processing microprocessor.
The mission of the SCDL is to forge a new paradigm for the rapid design of complex digital systems, digital signal and image processing, digital communications, and advanced processor systems in field programmable gate arrays (FPGA) and now reconfigurable system-on-chip (SoC) architectures utilizing behavioral analysis and synthesis and industry-standard digital design and embedded system computer aided (CAD) software tools.
Facilities for behavioral and hardware synthesis include the complete Integrated Synthesis Environment (ISE) and the Vivado design suite from Xilinx executing on Windows Engineering workstations. The SCDL is located in the College of Engineering Building on the Main Campus of Temple University, Philadelphia.
The SCDL is an educational facility with a mandate to meld the traditional threads of digital logic design to the SoC paradigm of both the FPGA and SoC architectures in both undergraduate and graduate Engineering education. Faculty and student resources are provided for this mission and for curriculum development.
The SCDL is a research facility that pursues innovative investigations and solicits tasks from industry with strict adherence to an Non-Disclosure Agreement (NDA), documentation, and timely completion of projects. SCDL trains talented undergraduate and graduate students in the SoC design methodology that utilizes hard processor intellectual property (IP) cores, reconfigurable SoC and soft core architectures on FPGA, on-chip busing arbitration architectures, and the integration of heterogeneous multiple processor real-time operating systems (RTOS).
An emphasis of the SCDL is the utilization of Xilinx Spartan, Virtex, Artix and Kintex field programmable gate arrays (FPGA) and Xilinx Zynq SoC devices and their ISE and Vivado tools in undergraduate and graduate courses as part of the Xilinx University Program. The SCDL is responsible for the undergraduate courses and laboratories in digital logic, microprocessor systems, embedded system design and advanced processors.
Contemporary graduate research in algorithms into hardware is focusing on parallel processing in the FPGA and SoC and advanced CAD tools and techniques.
The University supports the SCDL with the Office of the Vice Provost for Research. For further information on the research of the SCDL contact the Director: Dennis Silage, PhD firstname.lastname@example.org